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APL5910
1A, Ultra Low Dropout (0.12V Typical) Linear Regulator
Features
* * * * * * * * * * * * * *
Ultra Low Dropout - 0.12V (Typical) at 1A Output Current 0.8V Reference Voltage High Output Accuracy - 1.5% over Line, Load, and Temperature Range Fast Transient Response Adjustable Output Voltage Power-On-Reset Monitoring on Both VCNTL and VIN Pins Internal Soft-Start Current-Limit and Short Current-Limit Protections Thermal Shutdown with Hysteresis Open-Drain VOUT Voltage Indicator (POK) Low Shutdown Quiescent Current (< 30A ) Shutdown/Enable Control Function Simple SOP-8P Package with Exposed Pad Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APL5910 is a 1A ultra low dropout linear regulator. The IC needs two supply voltages, one is a control voltage (VCNTL) for the control circuitry, the other is a main supply voltage (VIN) for power conversion, to reduce power dissipation and provide extremely low dropout voltage. The APL5910 integrates many functions. A Power-OnReset (POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous operations. The functions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A POK indicates that the output voltage status with a delay time set internally. It can control other converter for power sequence. The APL5910 can be enabled by other power systems. Pulling and holding the EN voltage below 0.4V shuts off the output. The APL5910 is available in a SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance to extend power range of applications.
Applications
* * *
Motherboards, VGA Cards Notebook PCs Add-in Cards
Simplified Application Circuit
VCNTL
VIN
VCNTL POK POK VIN VOUT
Pin Configuration
POK EN VIN VCNTL 1 2 3 4 8 7 6 5 GND FB VOUT NC
VOUT
APL5910
EN EN GND FB
Enable
Optional
SOP-8P (Top View)
= Exposed Pad (connected to ground plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 1 www.anpec.com.tw
APL5910
Ordering and Marking Information
APL5910 Assembly Material Handling Code Temperature Range Package Code
APL5910 XXXXX
Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXX - Date Code
APL5910 KA :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VCNTL VIN VOUT Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) VOUT to GND Voltage POK to GND Voltage EN, FB to GND Voltage PD TJ TSTG TSDR Power Dissipation Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Rating -0.3 ~ 6 -0.3 ~ 6 -0.3 ~ VIN+0.3 -0.3 ~ 7 -0.3 ~ VCNTL+0.3 Internally Limited 150 -65 ~ 150 260 V W
Unit V V V
C C

C
Thermal Characteristics
Symbol JA JC Parameter Junction-to-Ambient Resistance in Free Air (Note 1) SOP-8P Junction-to-Case Resistance in Free Air (Note 2) SOP-8P Typical Value 50 20 Unit
o
C/W C/W
o
Note 1: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 2: The "Thermal-Pad Temperature" is measured on the PCB copper area connected to the thermal pad of package.
1 2 3 4 8 7 6 5
Measured Point PCB Copper
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APL5910
Recommended Operating Conditions
Symbol VCNTL VIN VOUT IOUT R2 COUT ESRCOUT TA TJ VCNTL Supply Voltage VIN Supply Voltage VOUT Output Voltage (when VCNTL-VOUT>1.4V) VOUT Output Current FB to GND IOUT=1A at 25% nominal VOUT VOUT Output Capacitance IOUT=0.5A at 25% nominal VOUT IOUT=0.25A at 25% nominal VOUT ESR of VOUT Output Capacitor Ambient Temperature Junction Temperature Parameter Range 3.0 ~ 5.5 1.0 ~ 5.5 0.8 ~ VIN - VDROP 0~1 1k ~ 24k 8 ~ 600 8 ~ 900 8 ~ 1100 0 ~ 200 -40 ~ 85 -40 ~ 125 m

Unit V V V A F
C
C
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.5V, VOUT=1.2V, and TA= -40 ~ 85oC, unless otherwise specified. Typical values are at TJ=25oC.
Symbol SUPPLY CURRENT IVCNTL ISD VCNTL Supply Current VCNTL Supply Current at Shutdown VIN Supply Current at Shutdown POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE VREF Reference Voltage Output Voltage Accuracy Load Regulation Line Regulation VOUT Pull-Low Resistance FB Input Current DROPOUT VOLTAGES VOUT=2.5V VDROP VIN-to-VOUT Dropout Voltage VCNTL=4.5V, IOUT=1A VOUT=1.8V VOUT=1.2V TJ=25oC TJ=-40~125oC TJ=25 C TJ=-40~125oC TJ=25oC TJ=-40~125oC
o
Parameter
Test Conditions
APL5910 Min. Typ. Max.
Unit
EN = VCNTL, IOUT=0A EN = GND EN = GND, VIN=5.5V
-
1.0 20 -
1.5 30 1
mA A A
2.5 0.8 FB=VOUT, IOUT=10mA,TJ=25oC IOUT= 0~1A, TJ= -40~125 C IOUT=0A ~1A IOUT=10mA, VCNTL= 3.0 ~ 5.5V VCNTL=3.3V,VEN=0V, VOUT<0.8V VFB=0.8V
o
2.7 0.4 0.9 0.5
2.9 1.0 -
V V
V
0.792 -1.5 -0.15 -100
0.8 0.06 85 -
0.808 +1.5 0.15 +0.15 100
V % % %/V nA
-
0.13 0.12 0.12 -
0.16 0.22 0.15 0.20 0.14 0.19 V
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APL5910
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.5V, VOUT=1.2V, and TA= -40 ~ 85oC, unless otherwise specified. Typical values are at TJ=25oC.
Symbol PROTECTIONS ILIM ISHORT
Parameter
Test Conditions
APL5910 Min. Typ. Max.
Unit
Current-Limit Level Short Current-Limit Level Short Current-Limit Blanking Time
TJ=25C TJ= -40 ~ 125 C VFB<0.2V From beginning of soft-start
1.7 1.4 0.6 0.5 -
2.1 0.4 1.6 170 50 0.8 80 5 0.6 92 8 0.25 10 2
2.5 1.1 1 94 0.4 4 ms
o
A
TSD
Thermal Shutdown Temperature TJ rising Thermal Shutdown Hysteresis
C C
o
ENABLE AND SOFT-START EN Logic High Threshold Voltage VEN rising EN Hysteresis EN Pull-High Current TSS VTHPOK Soft-Start Interval Rising POK Threshold Voltage POK Threshold Hysteresis POK Pull-Low Voltage POK Debounce Interval POK Delay Time POK sinks 5mA VFB0.3 90 1
POWER-OK AND DELAY
Pin Description
PIN NO. 1 NAME POK FUNCTION Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK voltage window. Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When left this pin open, an internal pull-up current (5A typical) pulls the EN voltage and enables the regulator. Main supply input pin for voltage conversions. A decoupling capacitor (10F recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The voltage on this pin is monitored for Power-On-Reset purpose Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (1F typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. No Connection. Output pin of the regulator. Connecting this pin to load and output capacitors (10F at least) is required for stability and improving transient response. The output voltage is programmed by the resistor-divider connected to FB pin. The VOUT can provide 1A (max.) load current to loads. During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET. Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator.
2
EN
3
VIN
4 5
VCNTL NC
6
VOUT
7
FB
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APL5910
Pin Description (Cont.)
PIN NO. 8 Exposed Pad NAME GND FUNCTION Ground pin of the circuitry. All voltage levels are measured with respect to this pin. P-Type Substrate connection of the chip. Connect this pad to system ground plane for good thermal conductivity.
Block Diagram
VCNTL
VCNTL 5A EN 0.8V POK
Thermal Shutdown
POR
PowerOn-Reset (POR)
Enable
Control Logic and Soft-Start Soft-Start Enabl e VIN
POR VREF 0.8V PWOK Dela y 90% VREF
Error Amplifier
Current-Limit and Short Current-Limit
VOUT ISEN GND
FB
Typical Application Circuit
VCNTL (+5V is preferred) CCNTL 1F 4 R3 5.1k POK 1 POK VCNTL VIN VOUT APL5910 EN GND R2 24k 8 FB 3 6 VOUT +1.2V / 1A 2 7 R1 12k COUT 10F (X5R/X7R Recommended) CIN 10F VIN +1.5V
EN Enable
C1 Optional (X5R/X7R Recommended)
10F: GRM31MR60J106KE19 Murata Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 5 www.anpec.com.tw
APL5910
Typical Operating Characteristics
Current-Limit vs. Junction Temperature
2.5 600 VOUT = 1.2V
Short Current-Limit vs. Junction Temperature
Short Current-Limit, ISHORT (mA)
550 500 450 400 350 300 250 200 VCNTL = 5V VCNTL = 3.3V
2.4 2.3
Current-Limit, ILIM (A)
2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 -50 -25 0
VCNTL = 5V
VCNTL = 3.3V
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (oC)
Junction Temperature (oC)
Dropout Voltage vs. Output Current
180 200 160 140 120 100 80 60 40 TJ = - 40X C 20 0 0 0.25 0.5 0.75 1 TJ = 0X C VCNTL = 5V VOUT = 1.2V 180 TJ = 125X C TJ = 75X C TJ = 25X C
Droput Voltage vs. Output Current
VCNTL = 3.3V VOUT = 1.2V
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
160 140 120 100 80 60 40 20 0 0 0.25 0.5
TJ = 125X C TJ = 75X C TJ = 25X C
TJ = 0X C TJ = - 40X C
0.75
1
Output Current, IOUT (A)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
200 180 220 TJ = 125X C TJ = 75X C TJ = 25X C VCNTL = 5V VOUT = 1.8V 200
Dropout Voltage vs. Output Current
VCNTL = 3.3V VOUT = 1.8V TJ = 125X C TJ = 75X C TJ = 25X C
Dropout Voltage, VDROP (mV)
Dropout Voltage, VDROP (mV)
160 140 120 100 80 60 40 20 0 0 0.25 0.5
180 160 140 120 100 80 60 40 20 0
TJ = 0X C TJ = - 40X C
TJ = 0X C TJ = - 40X C
0.75
1
0
0.25
0.5
0.75
1
Output Current, IOUT (A)
Output Current, IOUT (A)
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APL5910
Typical Operating Characteristics (Cont.)
Dropout Voltage vs. Output Current
220 200
Reference Voltage vs. Junction Temperature
0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 -50
Dropout Voltage, VDROP (mV)
180 160 140 120 100 80 60 40 20 0 0
TJ = 125X C TJ = 75X C TJ = 25X C
TJ = 0X C TJ = - 40X C 0.25 0.5 0.75 1
Reference Voltage, VREF (V)
VCNTL = 5V VOUT = 2.5V
-25
0
25
50
75
100
125
Output Current, IOUT (A)
Junction Temperature (oC)
VCNTL Power Supply Rejection Ratio (PSRR)
0 0 Power Supply Rejection Ratio (dB) VCNTL=4.6~5.4V VIN=1.5V VOUT=1.2V IOUT=1A CIN=COUT=10F -10 -20 -30 -40 -50 -60 -70 1000
VIN Power Supply Rejection Ratio (PSRR)
VCNTL=5V VIN=1.55V VINPK-PK=100mV VOUT=1.2V IOUT=1A COUT=10F
Power Supply Rejection Ratio (dB)
-10 -20 -30 -40 -50 -60 -70
-80 1000
10000
100000
1000000
10000
100000
1000000
Frequency (Hz)
Frequency (Hz)
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APL5910
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Power On
Power Off
1
VCNTL
VCNTL 1 VIN
VIN 2
2
VOUT 3 4 VPOK
VOUT 3 VPOK 4
COUT=10F, CIN=10F, RL=1.2 CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 5ms/Div
COUT=10F, CIN=10F, RL=1.2 CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 10ms/Div
Load Transient Response
Over Current Protection
VOUT
1 VOUT
1
IOUT
IOUT
4
4
IOUT =10mA to 1A to 10mA (rise / fall time = 1) COUT=10F, CIN=10F CH1: VOUT, 20mV/Div, AC CH4: IOUT, 0.5A/Div, DC TIME: 20s/Div
COUT=10F, CIN=10F, IOUT=1A to 2.3A CH1: VOUT, 1V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 50s/Div
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APL5910
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified.
Shutdown
Enable
VEN 1 VOUT
VEN 1
VOUT
2 VPOK 3 IOUT
2 VPOK 3
IOUT
4
4
COUT=10F, CIN=10F, RL=1.2 CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 1.0A/Div, DC TIME: 10s/Div
COUT=10F, CIN=10F, RL=1.2 CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 1.0A/Div, DC TIME: 0.5ms/Div
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APL5910
Function Description
Power-On-Reset A Power-On-Reset (POR) circuit monitors both of supply voltages on VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR voltage thresholds during powering on. The POR function also pulls low the POK voltage regardless of the output status when one of the supply voltages falls below its falling POR voltage threshold. Internal Soft-Start An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The typical soft-start interval is about 0.6ms. Output Voltage Regulation An error amplifier working with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit Protection The APL5910 monitors the current flowing through the output NMOS and limits the maximum current to prevent load and APL5910 from damages during current overload conditions. Short Current-Limit Protection The short current-limit function reduces the current-limit level down to 0.4A (typical) when the voltage on FB pin falls below 0.2V (typical) during current overload or shortcircuit conditions. The short current-limit function is disabled for successful start-up during soft-start interval. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5910. When the junction temperature exceeds +170oC, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start process after the junction temperature cools by 50oC,
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resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, the device power dissipation should be externally limited so that junction temperatures will not exceed +125C. Enable Control The APL5910 has a dedicated enable pin (EN). A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5A typical) to enable normal operation. It' not necess sary to use an external transistor to save cost. Power-OK and Delay The APL5910 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK voltage threshold (VTHPOK), an internal delay function starts to work. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate that the output is ok. As the VFB falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK (after a debounce time of 10s typical).
APL5910
Application Information
Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. Output Capacitor The APL5910 requires a proper output capacitor to maintain stability and improve transient response. The output capacitor selection is dependent upon ESR (equivalent series resistance) and capacitance of the output capacitor over the operating temperature. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as output capacitors. During load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5910 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5910 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limits the slew rate of the surge currents, more parasitic inductance needs, more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN is 10F at least. However, if the drop of the input voltage is not cared, the input capacitance can be less than 10F.
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More capacitance reduces the variations of the supply voltage on VIN pin. Setting The Output Voltage The output voltage is programmed by the resistor divider connected to FB pin. The preset output voltage is calculated by the following equation :
R1 VOUT = 0.8 1 + R2
........... (V)
where R1 is the resistor connected from VOUT to FB with Kelvin sensing connection and R2 is the resistor connected from FB to GND. A bypass capacitor (C1) may be connected with R1 in parallel to improve load transient response and stability.
APL5910
Layout Consideration (See figure 1)
1. Please solder the Exposed Pad on the system ground pad on the top-layer of PCBs. The ground pad must have wide size to conduct heat into the ambient air through the system ground plane and PCB as a heat sink. 2. Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for decoupling high-frequency ripples. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible for decoupling high-frequency ripples. 4. To place APL5910 and output capacitors near the load reduces parasitic resistance and inductance for excellent load transient reponse. 5. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure 1, must have wide tracks. 7. Place the R1, R2, and C1 near the APL5910 as close as possible to avoid noise coupling. 8. Connect the ground of the R2 to the GND pin by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 10. Connect one pin of the C1 to the VOUT pin for reliable feedback compensation. Figure 2
VCNTL CCNTL VCNTL VIN APL5910 VOUT C1
(Optional)
Thermal Consideration Refer to the figure 2, the SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top-layer ground plane. It is recommended to connect the top-layer ground pad to the internal ground plan by using vias. The copper of the ground plane on the top-layer conducts heat into the PCB and ambient air. Please enlarge the area of the top-layer pad and the ground plane to reduce the case-to-ambient resistance (CA).
1 2 3 4
SOP-8P
8 7 6 5
Internal ground plane
Ambient Air
Die
Exposed Pad
Top ground plane
PCB
Recommanded Minimum Footprint
CIN VIN VOUT COUT
0.024 0.072 8 7 6 5
0.212
GND R2
R1
Figure 1
1 2 0.050 3 4
Unit : Inch
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0.118
FB
0.138
Load
APL5910
Package Information
SOP-8P
D SEE VIEW A D1 THERMAL PAD E2 E1
E
e
b
h X 45
c
0.25 GAUGE PLANE SEATING PLANE VIEW A
0
A2 A1
A
L
S Y M B O L A A1 A2 b c D D1 E E1 E2 e h L 0
SOP-8P MILLIMETERS MIN. MAX. 1.60 0.00 1.25 0.31 0.17 4.80 2.25 5.80 3.80 2.00 1.27 BSC 0.25 0.40 0o 0.50 1.27 8o 0.010 0.016 0o 0.51 0.25 5.00 3.50 6.20 4.00 3.00 0.15 0.000 0.049 0.012 0.007 0.189 0.098 0.228 0.150 0.079 0.050 BSC 0.020 0.050 8o 0.020 0.010 0.197 0.138 0.244 0.157 0.118 MIN. INCHES MAX. 0.063 0.006
Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side.
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APL5910
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
SOP- 8P
T1 C d 12.4+2.00 13.0+0.50 330.0O .00 50 MIN. 2 1.5 MIN. -0.00 -0.20 P0 P1 P2 D0 D1 1.5+0.10 4.0O .10 8.0O .10 2.0O .05 0 0 0 1.5 MIN. -0.00
A
H
H A
T1
D
W
E1
W
F 5.5O .05 0
0 0 20.2 MIN. 12.0O .30 1.75O .10
T A0 B0 K0 0.6+0.00 6.40O .20 5.20O .20 2.10O .20 0 0 0 -0.40
(mm)
Devices Per Unit
Package Type SOP- 8P
Unit
Tape & Reel
Quantity
2500
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APL5910
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Reflow Condition (IR/Convection or VPR Reflow)
TP Ramp-up TL Tsmax tp Critical Zone TL to TP
Temperature
tL
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
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Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
15
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APL5910
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm Volume mm <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008
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www.anpec.com.tw

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